Chris Conger, M.S.

Ph.D. Student at The University of Florida

Department of Electrical and Computer Engineering
Research Assistant at the High-performance Computing and Simulation (HCS) Research Lab

Active member of CHREC, F4 project leader

 

Department of Electrical and Computer Engineering
University of Florida
PO Box 116200, 317 Larsen Hall
Gainesville, FL 32611-6200

 

Office Phone: (352) 392-9046

Home Phone:            (850) 445-1924

Email:                         conger@hcs.ufl.edu, banole@ufl.edu

 

Education

August, 2007 – Received Master of Science in Electrical & Computer Engineering from The University of Florida

May, 2003 –               Received Bachelor of Science in Electrical Engineering from The Florida State University

June, 2003 –                          Received Engineer Intern (#1100008336) certificate from the Florida Board of Professional Engineers, pre-requisite for earning a Professional Engineer (PE) license

 

Research Interests, Publications

Interests

  • Reconfigurable computing with FPGAs, Partial Reconfiguration
  • Parallel and fault-tolerant computing for space
  • High-performance embedded computing
  • High-speed serial interconnects

 

Journal papers

·        D. Bueno, C. Conger, and A. George, "RapidIO for Radar Processing in Advanced Space Systems," ACM Transactions on Embedded Computing Systems, accepted and in press.  Click here for a copy.

  • coming soon…

Conference papers

  • coming soon…
  • coming soon…
  • coming soon…
  • C. Conger, A. Jacobs, and A. George, "Application-level Benchmarking with Synthetic Aperture Radar," Proc of High-Performance Embedded Computing (HPEC) Workshop, MIT Lincoln Lab, Lexington, MA, Sep. 18-20, 2007, to appear.  Click [here] for a copy.
  • C. Conger, D. Bueno, and A. George, “Experimental Analysis of Multi-FPGA Architectures over RapidIO for Space-Based Radar Processing,” Proc. of High-Performance Embedded Computing (HPEC) Workshop, MIT Lincoln Lab, Lexington, MA, Sep. 19-21, 2006.  Click [here] for a copy.
  • D. Bueno, C. Conger, A. Leko, I. Troxel, and A. George, “RapidIO-based Space Systems Architectures for Synthetic Aperture Radar and Ground Moving Target Indicator,” Proc. of High-Performance Embedded Computing (HPEC) Workshop, MIT Lincoln Lab, Lexington, MA, Sep. 20-22, 2005.  Click [here] for a copy.
  • C. Conger, I. Troxel, D. Espinosa, V. Aggarwal, and A. George, “NARC: Network-Attached Reconfigurable Computing for High-performance, Network-based Applications,” Proc. of 8th International Conference on Military and Aerospace Programmable Logic Devices (MAPLD), Washington D.C., Sep. 6-8, 2005.  Click [here] for a copy.
  • D. Bueno, A. Leko, C. Conger, I. Troxel, and A. George, "Simulative Analysis of the RapidIO Embedded Interconnect Architecture for Real-Time, Network-Intensive Applications," Proc. of 29th IEEE Conference on Local Computer Networks (LCN) via the IEEE Workshop on High-Speed Local Networks (HSLN), Tampa, FL, Nov. 16-18, 2004.  Click [here] for a copy.
  • D. Bueno, C. Conger, A. Leko, I. Troxel and A. George, "Virtual Prototyping and Performance Analysis of RapidIO-based System Architectures for Space-Based Radar," Proc. of High-Performance Embedded Computing (HPEC) Workshop, MIT Lincoln Lab, Lexington, MA, Sep. 28-30, 2004.  Click [here] for a copy.

Master’s thesis

  • C. Conger, “Reconfigurable Computing with RapidIO for Space-Based Radar Processing,” Master’s Thesis, Dept. of Electrical and Computer Engineering, University of Florida, August 2007.  Click [here] for a copy.

Doctoral dissertation

  • coming later…

 

Spring 2008 Class/Lab Schedule

 

                      

 

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