Scalable Coherent Interface (SCI) Activities in the HCS Research Lab

Overview

IEEE Standard 1596-1992 Scalable Coherent Interface (SCI) is based on a structure or fabric of scalable register-insertion rings with shared-memory split transactions. The SCI standard supports up to 64K nodes in a variety of topologies, including rings, switched rings, and tori. SCI networks are unique in their support for shared-memory and message-passing communication, indirect and direct switching topologies, multiple outstanding transactions, extremely low application-level latency, and high effective throughput.

For a node in an SCI network, when a request or response packet enters over the input link, it is relayed by an address decoder to a request or response input FIFO, respectively, if the packet's destination address matches the address of the node. If it does not match, the packet is relayed through a bypass FIFO to return to the network via the output link. Similarly, requests and responses made by the host are queued and then multiplexed onto the output link along with the output of the bypass FIFO.

The High-performance Computing and Simulation (HCS) Research Laboratory has been conducting research on and with Scalable Coherent Interface (SCI) since 1995. Currently, there are a number of research and development activities being conducted, both experimental and simulative. The primary sponsors for these activities are the National Security Agency (NSA), Dolphin Interconnect, and Scali, and we gratefully acknowledge their support.

SCI Publications

Past research with SCI has led to a number of journal and conference papers. Please see our publications web page for papers with detailed results from this research. Here is a sample of some of our recent SCI-based research papers:

R. Todd, M. Chidester, and A. George, "Comparative Performance Analysis of Directed Flow Control for Real-Time SCI," Computer Networks, Vol. 37, No. 4, Nov. 2001, pp. 391-406.
M. Sarwar and A. George, "Simulative Performance Analysis of Distributed Switching Fabrics for SCI-based Systems," Microprocessors and Microsystems, Vol. 24, No. 1, Mar. 2000, pp. 1-11.
M. Burns, A. George, and B. Wallace, "Modeling and Simulative Performance Analysis of SMP and Clustered Computer Architectures," Simulation, Vol. 74, No. 2, Feb. 2000, pp. 84-96.
A. George, J. Markwell, R. Fogarty, and M. Miars, "An Integrated Simulation Environment for Parallel and Distributed System Prototyping," Simulation, Vol. 72, No. 5, May 1999, pp. 283-294.
M. Sarwar, A. George, and D. Collins, "Simulative Reliability Analysis of SCI Ring-Based Topologies," Proc. of IEEE Conference on Local Computer Networks (LCN), Tampa, FL, November 8-10, 2000.
M. Sarwar and A. George, "Simulative Analysis of Fault-Tolerant Distributed Switching Fabrics for SCI," Proc. of 11th Intnl. SCI Workshop (SCIzzL), Santa Clara, California, March 1999, pp. 5-22.
A. George, R. Todd, and W. Phipps, "Experimental Analysis of Communications Interfaces for High-Performance Clusters," Proc. High-Performance Computing Symposium (HPC'98), Boston, MA, April 5-9, 1998, pp. 283-288.

SCI Theses and Dissertations

Past research with SCI has also led to a number of graduate theses and dissertations, including:

Mark W. Burns, "Modeling and Simulative Analysis of Symmetric Multiprocessor and Clustered Computer Architectures," MSECE Thesis, Major Professor: A. George, Spring 1999.
Matthew C. Chidester, "Specification and Simulation of a Directed Flow Control for Ring-Based, Real-Time Networking," MSECE Thesis, Major Professor: A. George, Summer 1998.
Matthew C. Chidester, "Parallel Simulation and Multiple-Path Execution Techniques for Chip-Multiprocessor Architectures," Ph.D. Dissertation, Major Professor: A. George, Summer 2001.
Ryan B. Fogarty, "An Integrated Simulation Environment for Parallel and Distributed System Prototyping," MSECE Thesis, Major Professor: A. George, Fall 1998.
Damian M. Gonzalez, "Performance Modeling and Evaluation of Topologies for Low-Latency SCI Systems," MSECE Thesis, Major Professor: A. George, Fall 2000.
William A. Phipps, "A Lightweight Thread Synchronization and Communication Subsystem for the Scalable Cluster Architecture Latency-hiding Environment," MSEE Thesis, Major Professor: A. George, Spring 1997.
Mushtaq A. Sarwar, "On the Performance and Reliability of Fault-Tolerant Scalable Coherent Interface Networks," Ph.D. Dissertation, Major Professor: A. George, Fall 1999.
Robert W. Todd, "A Simulation Case Study of Proposed Real-Time Protocols based on the Scalable Coherent Interface," MSEE Thesis, Major Professor: A. George, Summer 1996.

Current SCI Activities

analytical modeling with experimental calibration of latency and throughput for scalable SCI-based systems
parallel simulation of chip-multiprocessor (CMP) architectures using SCI clusters
experimental performance analysis of SCI as a PC cluster interconnect
simulative research with SCI as a chip-area interconnect for CMPs
comparative analysis of SCI performance vs. other high-speed networks

The experimental research with SCI is conducted in the CARRIER cluster supercomputer. In CARRIER, SCI is currently prominent in the Eta cluster with a new 4x4 SCI torus "Wulfkit" operating at 667MB/s (i.e. 5.3Gb/s) link speed with PCI64/66 interfaces, and in the Zeta cluster with a 3x3 SCI torus operating at 500MB/s (i.e. 4Gb/s) link speed with PCI32/33 interfaces.

For more information about SCI research experience, capabilities, and opportunities in the HCS Research Lab, please contact the lab director, Dr. George.