RapidIO Activities at the University of Florida

Researchers in the HCS Lab are pursuing several research tasks related to the RapidIO Embedded Systems Interconnect. RapidIO is an emerging standard for high-performance switched interconnection of processors, memory, and other components in embedded systems. RapidIO is an open standard, controlled by the RapidIO Trade Association. There are serial and parallel standards, with the parallel version providing higher data rates and the serial version providing a lower pin-count. The RapidIO protocol's defining characteristic is that it is defined with simplicity in mind, so that it does not take up an exorbitant amount of real-estate on embedded devices. It is a three-layer protocol, with the Logical Layer providing the specification for end-to-end transactions, the Transport Layer providing simple routing guidelines, and the Physical Layer determining the link-level communication properties such as type of flow control and serial vs. parallel communication. The RapidIO physical layer protocols also provide simple but effective methods for error correction and detection, which is critical for an embedded system in a potentially harsh environment.

The HPN and MS groups of the HCS Lab are the primary groups responsible for research in RapidIO, under sponsorship from Honeywell Space Systems in Clearwater, FL. In 2003 and 2004, work in the HCS lab focused on the modeling and simulation of RapidIO hardware and related applications using MLDesigner. Our primary interest has been next-generation space-based radar algorithms, such as Ground Moving Target Indicator (GMTI) and Synthetic Aperture Radar (SAR). As of Spring 2005, there are several concurrent focal points for this work. The first area is the development of a RapidIO testbed using Xilinx VirtexII Pro FPGA chips and boards, and a Tundra 4-port parallel RapidIO switch. This testbed will be used to calibrate our simulation models and provide the means for more complex simulation experiments using RapidIO hardware and advanced algorithms running on the FPGAs and/or embedded PowerPCs. In addition, simulation work is ongoing in the area of network fault tolerance for RapidIO space systems. Previous space systems were bus-based and accomplish fault-tolerance by complete redundancy in the network. A switched network such as RapidIO provides the potential for fault-tolerance through other means such as redundant paths between nodes, although the behavior is not defined in the RapidIO specification. This research will seek to find the optimal method for providing fault-tolerance in a RapidIO network. Simulation and experimental research is also ongoing in the area of GMTI, SAR, and other payload-processing type applications for RapidIO space systems.

RapidIO-related HCS Lab Publications

• D. Bueno, C. Conger, A. Leko, I. Troxel and A. George, "RapidIO-based Space System Architectures for Synthetic Aperture Radar and Ground Moving Target Indicator," Proc. of High-Performance Embedded Computing (HPEC) Workshop, MIT Lincoln Lab, Lexington, MA, Sep. 20-22, 2005. Click here for a copy of the abstract.

• D. Bueno, A. Leko, C. Conger, I. Troxel, and A. George, "Simulative Analysis of the RapidIO Embedded Interconnect Architecture for Real-Time, Network-Intensive Applications," Proc. of 29th IEEE Conference on Local Computer Networks (LCN) via the IEEE Workshop on High-Speed Local Networks (HSLN), Tampa, FL, Nov. 16-18, 2004. Click here for a PDF copy.

• D. Bueno, C. Conger, A. Leko, I. Troxel and A. George, "Virtual Prototyping and Performance Analysis of RapidIO-based System Architectures for Space-Based Radar," Proc. of High-Performance Embedded Computing (HPEC) Workshop, MIT Lincoln Lab, Lexington, MA, Sep. 28-30, 2004. Click here for a copy of the PowerPoint presentation.

RapidIO Testbed Components

• 2VP20-FF1152 -- Xilinx Virtex-II Pros
• HW-AFX-FF1152-300 -- Xilinx Virtex-II Pro Development Boards
• Tsi500 -- Tundra 4-port Parallel RapidIO Switch
• LA5580 -- Link Instruments 80-channel, 500MSa Logic Analyzer
• Xilinx LogiCORE 8-bit LVDS Parallel PHY Layer RapidIO Core
• Xilinx LogiCORE Logical I/O and Transport Layer RapidIO Core

Related RapidIO Links

• RapidIO Trade Association
• Tundra
• Xilinx RapidIO Information and Cores