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Reconfigurable Computing

Conference papers:

1. K. Shih, A. Balachandran, K. Nagarajan, B. Holland, C. Slatton, and A. George, "Fast Real-time LIDAR Processing on FPGAs," Proc. of 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), Las Vegas, NV, July 14-17, 2008, to appear.
2. A. Jacobs, G. Cieslewski, C. Reardon, and A. George, "Multiparadigm Computing for Space-Based Synthetic Aperture Radar," Proc. of 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), Las Vegas, NV, July 14-17, 2008, to appear.
3. C. Conger, A. Gordon-Ross, and A. George, "FPGA Design Framework for Partial Run-Time Reconfiguration," Proc. of 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), Las Vegas, NV, July 14-17, 2008, to appear.
4. J. Curreri, S. Koehler, B. Holland, and A. George, "Performance Analysis with High-Level Languages for High-Performance Reconfigurable Computing," Proc. of 16th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Palo Alto, CA, Apr. 14-15, 2008. Click here for an electronic copy.
5. K. Nagarajan, B. Holland, C. Slatton, and A. George, "Scalable and Portable Architecture for Probability Density Function Estimation on FPGAs," Proc. of 16th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Palo Alto, CA, Apr. 14-15, 2008 (short paper). Click here for an electronic copy.
6. H. Su, M. Billingsley, and A. George, "Parallel Performance Wizard: A Performance Analysis Tool for Partitioned Global-Address-Space Programming," 9th IEEE International Workshop on Parallel & Distributed Scientific and Engineering Computing (PDSEC) of IPDPS 2008, Miami, FL, Apr. 14-15, 2008. Click here for an electronic copy.
7. K. Sabhanatarajan, A. Gordon-Ross, M. Oden, M. Navada, and A. George, "Smart-NICs: Power Proxying for Reduced Power Consumption in Network Edge Devices," Proc. of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Montpellier, France, Apr. 7-9, 2008. Click here for an electronic copy.
8. A. George, "Reformation and Formulation: Key Challenges for Reconfigurable Supercomputing," Proc. of Many-core and Reconfigurable Supercomputing Conference (MRSC), Belfast, Ireland, Apr. 1-3, 2008 (keynote). Click here for an electronic copy.
9. B. Holland and A. George, "Memory-Driven Algorithm Mapping of Molecular Dynamics for High-Performance Reconfigurable Computers," Proc. of Many-core and Reconfigurable Supercomputing Conference (MRSC), Belfast, Ireland, Apr. 1-3, 2008.
10. A. George, "Reconfigurable Computing: the Emerging Paradigm for High-Performance Computing," SIAM Conference on Parallel Processing for Scientific Computing, Atlanta, GA, Mar. 12-14, 2008 (invited). Click here for an electronic copy.
11. A. Jacobs, C. Conger, and A. George, "Multiparadigm Space Processing for Hyperspectral Imaging," Proc. of IEEE Aerospace Conference, Big Sky, MT, Mar. 1-8, 2008, to appear. Click here for an electronic copy.
12. A. George, "CHREC: the New Industry/University Center for High-Performance Reconfigurable Computing," Proc. of Non-Conventional Computing Conference (NCCC), Orlando, FL, Feb. 6-7, 2008 (invited). Click here for an electronic copy.
13. B. Holland, K. Nagarajan, S. Merchant, H. Lam, and A. George, "Lessons Learned with Performance Prediction and Design Patterns on Molecular Dynamics," Proc. Military and Aerospace FPGA and Applications (MAFA) Meeting, Palm Beach, FL, Nov. 27-29, 2007. Click here for an electronic copy.
14. H. Su, M. Billingsley, S. Koehler, J. Curreri, and A. George, "Parallel Performance Wizard: A Generalized Performance Analysis Tool," SC 2007, Reno, NV, Nov. 11-14, 2007 (poster).
15. B. Holland, K. Nagarajan, C. Conger, A. Jacobs, and A. George, "RAT: A Methodology for Predicting Performance in Application Design Migration to FPGAs," Proc. of High-Performance Reconfigurable Computing Technologies & Apps Workshop (HPRCTA 2007) of SC 2007, Reno, NV, Nov. 11-14, 2007. Click here for an electronic copy.
16. C. Conger, A. Jacobs, and A. George, "Application-level Benchmarking with Synthetic Aperture Radar," Proc of High-Performance Embedded Computing (HPEC) Workshop, MIT Lincoln Lab, Lexington, MA, Sep. 18-20, 2007. Click here for an electronic copy.
17. R. Hymel, A. George, and H. Lam, "Evaluating Partial Reconfiguration for Embedded FPGA Applications," Proc of High-Performance Embedded Computing (HPEC) Workshop, MIT Lincoln Lab, Lexington, MA, Sep. 18-20, 2007 (short paper). Click here for an electronic copy.
18. A. George, "Reconfigurable Computing: From Satellites to Supercomputers," Proc. of Reconfigurable Systems Summer Institute 2007 (RSSI), Urbana, IL, July 17-20, 2007 (keynote). Click here for an electronic copy.
19. S. Koehler, J. Curreri, and A. George, "Challenges for Performance Analysis in High-Performance Reconfigurable Computing," Proc. of Reconfigurable Systems Summer Institute 2007 (RSSI), Urbana, IL, July 17-20, 2007. Click here for an electronic copy.
20. E. Grobelny, C. Reardon, A. Jacobs, and A. George, "Simulation Framework for Performance Prediction in the Engineering of RC Systems and Applications," Proc. of 2007 International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), Las Vegas, NV, June 25-28, 2007. Click here for an electronic copy.
21. G. Cieslewski, A. Jacobs, A. George, "Fault-Tolerant 2D Fourier Transform with Checksum Encoding," Proc. of IEEE Aerospace Conference, Big Sky, MT, Mar. 3-10, 2007. Click here for an electronic copy.
22. C. Conger, D. Bueno, and A. George, "Experimental Analysis of Multi-FPGA Architectures over RapidIO for Space-Based Radar Processing," Proc of High-Performance Embedded Computing (HPEC) Workshop, MIT Lincoln Lab, Lexington, MA, Sep. 19-21, 2006 (short paper). Click here for an electronic copy.
23. B. Holland, J. Greco, I. Troxel, G. Barfield, V. Aggarwal, and A. George, "Compile- and Run-time Services for Distributed Heterogeneous Reconfigurable Computing," Proc. of International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), Las Vegas, NV, June 26-29, 2006 (selected as distinguished research paper). Click here for a PDF copy.
24. J. Greco, G. Cieslewski, A. Jacobs, I. Troxel, and A. George, "Hardware/Software Interface for High-Performance Space Computing with FPGA Coprocessors," Proc. of IEEE Aerospace Conference, Big Sky, Montana, March 4-11, 2006. Click here for a PDF copy.
25. V. Aggarwal, A. George, and K. Slatton, "Reconfigurable Computing with Multiscale Data Fusion for Remote Sensing," Proc. of ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey, CA, February 22-24, 2006 (poster paper).
26. R. Subramaniyan, I. Troxel, A. George and M. Smith, "Simulative Analysis of Dynamic Scheduling Heuristics for FPGA-based Reconfigurable Computing of Parallel Applications," Proc. of ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey, CA, February 22-24, 2006 (poster paper).
27. C. Conger, I. Troxel, D. Espinoza, V. Aggarwal, and A. George, "NARC: Network-Attached Reconfigurable Computing for High-performance, Network-based Applications," Proc. of 8th International Conference on Military and Aerospace Programmable Logic Devices (MAPLD), Washington, DC, September 7-9, 2005. Click here for a PDF copy of the abstract, and click here for a copy of the PowerPoint abstract.
28. R. DeVille, V. Aggarwal, I. Troxel, and A. George, "Design and Tradeoff Analysis of JPEG2000 on Hardware-Reconfigurable Systems," Proc. of 8th International Conference on Military and Aerospace Programmable Logic Devices (MAPLD), Washington, DC, September 7-9, 2005. Click here for a PDF copy of the abstract, and click here for a copy of the PowerPoint presentation.
29. B. Holland, M. Vacas, V. Aggarwal, R. DeVille, I. Troxel, and A. George, "Survey of C-based Application Mapping Tools for Reconfigurable Computing," Proc. of 8th International Conference on Military and Aerospace Programmable Logic Devices (MAPLD), Washington, DC, September 7-9, 2005. Click here for a PDF copy of the abstract, and click here for a copy of the PowerPoint presentation.
30. R. DeVille, I. Troxel, and A. George, "Performance Monitoring for Run-time Management of Reconfigurable Devices," International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), Las Vegas, NV, June 27-30, 2005. Click here for a PDF copy.
31. D. Bueno, A. Leko, C. Conger, I. Troxel, and A. George, "Simulative Analysis of the RapidIO Embedded Interconnect Architecture for Real-Time, Network-Intensive Applications," Proc. of 29th IEEE Conference on Local Computer Networks (LCN) via the IEEE Workshop on High-Speed Local Networks (HSLN), Tampa, FL, Nov. 16-18, 2004. Click here for a PDF copy.
32. D. Bueno, C. Conger, A. Leko, I. Troxel and A. George, "Virtual Prototyping and Performance Analysis of RapidIO-based System Architectures for Space-Based Radar," Proc. of High-Performance Embedded Computing (HPEC) Workshop, MIT Lincoln Lab, Lexington, MA, Sep. 28-30, 2004. Click here for a copy of the PowerPoint presentation.
33. V. Aggarwal, I. Troxel, and A. George, "Design and Analysis of Parallel N-Queens on Reconfigurable Hardware with Handel-C and MPI," Proc. of 7th International Conference on Military and Aerospace Programmable Logic Devices (MAPLD), Washington, DC, September 8-10, 2004. Click here for a PDF copy of the abstract, and click here for a copy of the PowerPoint presentation.
34. I. Troxel, A. Jacob, A. George, R. Subramaniyan, and M. Radlinski, "CARMA: A Comprehensive Management Framework for High-Performance Reconfigurable Computing," Proc. of 7th International Conference on Military and Aerospace Programmable Logic Devices (MAPLD), Washington, DC, September 8-10, 2004. Click here for a PDF copy of the abstract, and click here for a copy of the PowerPoint presentation.
35. A. Jacob, I. Troxel, and A. George, "Distributed Configuration Management for Reconfigurable Cluster Computing," Proc. of International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), Las Vegas, NV, June 21-24, 2004. Click here for a PDF copy of this short paper, and click here for a copy of the long version.
36. I. Troxel, A. George, and S. Oral, "Design and Analysis of a Dynamically Reconfigurable Network Processor," Proc. of 27th IEEE Conference on Local Computer Networks (LCN), Tampa, FL, November 6-8, 2002. Click here for a PDF copy.

Journal papers:

1. S. Koehler, J. Curreri, and A. George, "Performance Analysis Challenges and Framework for High-Performance Reconfigurable Computing," Parallel Computing (special issue on RC), Vol. 34, No. 4, May 2008, pp. 217-230. Click here for an electronic copy.
2. D. Bueno, C. Conger, A. George, A. Leko, and I. Troxel, "RapidIO for Radar Processing in Advanced Space Systems," ACM Transactions on Embedded Computing Systems, Vol. 7, No. 1, Dec. 2007, pp. 1:1-1:38. Click here for an electronic copy.
3. E. Grobelny, D. Bueno, I. Troxel, A. George, and J. Vetter, "FASE: A Framework for Scalable Performance Prediction of HPC Systems and Applications," Simulation: Transactions of The Society for Modeling and Simulation International, Vol. 83, No. 10, Oct. 2007, pp. 721-745. Click here for an electronic copy.
4. I. Troxel and A. George, "Adaptable and Autonomic Management System for Dependable Aerospace Computing," Journal of Autonomic and Trusted Computing, accepted and in press. Click here for an electronic copy.
5. I. Troxel, E. Grobelny, and A. George, "System Management Services for High-Performance In-situ Aerospace Computing," AIAA Journal of Aerospace Computing, Information, and Communication, Vol. 4, No. 2, February 2007, pp. 636-656. Click here for an electronic copy.
6. M. Chidester, A. George, and M. Radlinski, "Multiple-Path Execution for Chip Multiprocessors," Journal of Systems Architecture, Vol. 49, No. 1, Feb. 2003, pp. 33-52. Click here for an electronic copy.
7. M. Chidester and A. George, "Parallel Simulation of Chip-Multiprocessor Architectures," ACM Transactions on Modeling and Computer Simulation, Vol. 12, No. 3, July 2002, pp. 176-200. Click here for an electronic copy.

Dissertations and theses:

1. Vikas Aggarwal, "Remote Sensing and Imaging in a Reconfigurable Computing Environment," MSECE Thesis, Major Professor: K. Slatton and A. George, Summer 2005.
2. Aju Jacob, "Distributed Configuration Management for Reconfigurable Cluster Computing," MSECE Thesis, Major Professor: A. George, Summer 2004.
3. Ian A. Troxel, "Design and Analysis of a Dynamically Reconfigurable Network Processor," MSECE Thesis, Major Professor: A. George, Fall 2002.
4. Christopher J. Drake, "A Reconfigurable Node Architecture for a Cryptanalytic Cluster Computer System," BSCE Honors Thesis, Major Professor: A. George, Summer 2002.
5. Matthew C. Chidester, "Parallel Simulation and Multiple-Path Execution Techniques for Chip-Multiprocessor Architectures," Ph.D. Dissertation, Major Professor: A. George, Summer 2001.