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Reconfigurable Computing (RC) is a rapidly developing field that has begun to solidify over the last decade. RC techniques have been applied to high-performance computing designs to demonstrate increases in performance at decreased cost compared to traditional designs. A realization of this fact by academic, government and industry research labs has spawned a great deal of research in a broad spectrum of fields. An RC system uses reconfigurable hardware to augment its processor, thus achieving higher performance. The reconfigurable hardware, FPGAs for most COTS systems, is configured to yield the optimum performance for a given application. FPGAs and reconfigurable computing techniques have been shown to accelerate a variety of applications. For example, data encryption and signal processing applications are able to leverage both parallelism and fine-grained data manipulation inherent in RC systems. RC designs endeavor to merge the flexibility of processors with the raw performance power of ASICs.

The RC group in the HCS lab at UF is working to remain abreast of all major topics within the RC design space while actively pursuing several key directions:

• Algorithm taxonomy and mapping
• Intra-FPGA control structure taxonomy
• Modeling and simulation of RC-based systems for HPC
• RC/HPC management framework (CARMA)
• Statistics monitoring/aggregation and reporting in RC systems
• Configuration management techniques
• Active networking
• Satellite-based RC systems (radiation environments)

Comprehensive Approach to Reconfigurable Management Architecture (CARMA): Of these many exciting pursuits, the RC management framework for HPC is the group's capstone project. The extension of RC systems to high-performance computing, both general- and special-purpose, leads to new architecture and design considerations. A major task of the RC group is exploring these design options and discovering meaningful performance trade-offs. This exploration not only characterizes preexisting architectures but also gives birth to novel architectures. However, a system of COTS-based processing nodes connected via a high-performance network provides a scalable cost-effective solution for constructing RC systems. Each node in the sysetm is augmented with reconfigurable processing elements (RPE), consisting of one or more FPGAs on a PCI bus card. The processor typically performs the operations that cannot be done efficiently in the reconfigurable logic, such as data-dependent control and memory access, while the computationally complex functionality is mapped to the reconfigurable hardware.

Previously designed network-based RC systems have used FPGAs in high-performance computing, but these systems are typically centralized, tightly-coupled, batch-processing systems. The creation of a high-fidelity, distributed management framework for RC-enhanced systems is currently underway. Key to our success is the leveraging of existing systems services for management, resource monitoring and fault tolerance and building upon the many strengths and years of experience in high-performance computing and networking in the HCS Lab. The RC Group aims to extend such system tools in order to fashion a framework and new set of services for the management and exploitation of RC systems for applications of critical importance.