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Modeling and Simulation

Conference papers:

1. S. Merchant, B. Holland, C. Reardon, A. George, H. Lam, G. Stitt, et al., "Strategic Challenges for Application Development Productivity in Reconfigurable Computing," Proc. of National Aerospace & Electronics Conference (NAECON), Dayton, OH, July 16-18, 2008. Click here for an electronic copy.
2. A. Jacobs, G. Cieslewski, C. Reardon, and A. George, "Multiparadigm Computing for Space-Based Synthetic Aperture Radar," Proc. of 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), Las Vegas, NV, July 14-17, 2008. Click here for an electronic copy.
3. E. Grobelny, C. Reardon, A. Jacobs, and A. George, "Simulation Framework for Performance Prediction in the Engineering of RC Systems and Applications," Proc. of 2007 International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), Las Vegas, NV, June 25-28, 2007. Click here for an electronic copy.
4. D. Bueno, C. Conger, A. Leko, I. Troxel and A. George, "RapidIO-based Space System Architectures for Synthetic Aperture Radar and Ground Moving Target Indicator," Proc. of High-Performance Embedded Computing (HPEC) Workshop, MIT Lincoln Lab, Lexington, MA, Sep. 20-22, 2005. Click here for a copy of the abstract.
5. D. Bueno, A. Leko, C. Conger, I. Troxel, and A. George, "Simulative Analysis of the RapidIO Embedded Interconnect Architecture for Real-Time, Network-Intensive Applications," Proc. of 29th IEEE Conference on Local Computer Networks (LCN) via the IEEE Workshop on High-Speed Local Networks (HSLN), Tampa, FL, Nov. 16-18, 2004. Click here for a PDF copy.
6. D. Bueno, C. Conger, A. Leko, I. Troxel and A. George, "Virtual Prototyping and Performance Analysis of RapidIO-based System Architectures for Space-Based Radar," Proc. of High-Performance Embedded Computing (HPEC) Workshop, MIT Lincoln Lab, Lexington, MA, Sep. 28-30, 2004. Click here for a copy of the PowerPoint presentation.
7. G. Schorcht, I. Troxel, K. Farhangian, P. Unger, D. Zinn, C. Mick, A. George, and H. Salzwedel, "System-Level Simulation Modeling with MLDesigner," Proc. of 11th IEEE/ACM International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems (MASCOTS), Orlando, FL, October 12-15, 2003. Click here for a PDF copy.
8. I. Troxel, A. George, and S. Oral, "Design and Analysis of a Dynamically Reconfigurable Network Processor," Proc. of 27th IEEE Conference on Local Computer Networks (LCN), Tampa, FL, November 6-8, 2002. Click here for a PDF copy.
9. M. Sarwar, A. George, and D. Collins, "Simulative Reliability Analysis of SCI Ring-Based Topologies," Proc. of IEEE Conference on Local Computer Networks (LCN), Tampa, FL, November 8-10, 2000. Click here for a PDF copy.
10. P. Sutherland, T. Thomas, L. Hawkes, and A. George, "Hypercube-based Multicast over an ATM LAN Virtual Topology with Hardware Support," Proc. of 4th Multiconf. on Systematics, Cybernetics and Informatics (SCI2000) and 6th Intnl. Conf. on Info. Systems, Orlando, Florida, July 23-26, 2000.
11. M. Sarwar and A. George, "Simulative Analysis of Fault-Tolerant Distributed Switching Fabrics for SCI," Proc. of 11th Intnl. SCI Workshop (SCIzzL), Santa Clara, California, March, 1999. Click here for a PDF copy.
12. A. George, M. Miars, R. Todd, and W. Rosen, "Modeling and Simulation of Processors and Networks for Smart Navy Aircraft Components and Systems," Proc. 8th IEEE Southeastern Symposium on System Theory, Baton Rouge, LA, March, 1996. Click here for a PDF copy.

Journal papers:

1. C. Reardon, E. Grobelny, A. George, and G. Wang, "A Simulation Framework for Rapid Analysis of Reconfigurable Computing Systems," ACM Transactions on Reconfigurable Technology and Systems (TRETS), accepted and in press.
2. D. Bueno, C. Conger, and A. George, "Optimizing RapidIO Architectures for Onboard Processing," ACM Transactions on Embedded Computing Systems (TECS), accepted and in press.
3. B. Holland, K. Nagarajan, and A. George, "RAT: RC Amenability Test for Rapid Performance Prediction," ACM Transactions on Reconfigurable Technology and Systems (TRETS), Vol. 1, No. 4, Jan. 2009, pp. 22:1-22:31. Click here for an electronic copy.
4. D. Bueno, C. Conger, A. George, A. Leko, and I. Troxel, "RapidIO for Radar Processing in Advanced Space Systems," ACM Transactions on Embedded Computing Systems (TECS), Vol. 7, No. 1, Dec. 2007, pp. 1:1-1:38. Click here for an electronic copy.
5. E. Grobelny, D. Bueno, I. Troxel, A. George, and J. Vetter, "FASE: A Framework for Scalable Performance Prediction of HPC Systems and Applications," Simulation: Transactions of The Society for Modeling and Simulation International, Vol. 83, No. 10, Oct. 2007, pp. 721-745. Click here for an electronic copy.
6. M. Chidester, A. George, and M. Radlinski, "Multiple-Path Execution for Chip Multiprocessors," Journal of Systems Architecture, Vol. 49, No. 1, Feb. 2003, pp. 33-52. Click here for an electronic copy.
7. M. Chidester and A. George, "Parallel Simulation of Chip-Multiprocessor Architectures," ACM Transactions on Modeling and Computer Simulation, Vol. 12, No. 3, July 2002, pp. 176-200. Click here for an electronic copy.
8. D. Collins and A. George, "Parallel and Sequential Job Scheduling in Heterogeneous Clusters: A Simulation Study using Software in the Loop," Simulation, Vol. 77, No. 6, Dec. 2001, pp. 169-184. Click here for an electronic copy.
9. R. Todd, M. Chidester, and A. George, "Comparative Performance Analysis of Directed Flow Control for Real-Time SCI," Computer Networks, Vol. 37, No. 4, Nov. 2001, pp. 391-406. Click here for an electronic copy.
10. D. Gonzalez, A. George, and M. Chidester, "Performance Modeling and Evaluation of Topologies for Low-Latency SCI Systems," Microprocessors and Microsystems, Vol. 25, No. 7, Oct. 2001, pp. 343-356. Click here for an electronic copy.
11. S. Ranganathan, A. George, R. Todd, and M. Chidester, "Gossip-Style Failure Detection and Distributed Consensus for Scalable Heterogeneous Clusters," Cluster Computing, Vol. 4, No. 3, July 2001, pp. 197-209. Click here for an electronic copy.
12. A. George and R. VanLoon, "High-Fidelity Modeling and Simulation of Myrinet System Area Networks," International Journal of Modeling and Simulation, Vol. 21, No. 1, Jan. 2001, pp. 40-50. Click here for an electronic copy.
13. M. Sarwar and A. George, "Simulative Performance Analysis of Distributed Switching Fabrics for SCI-based Systems," Microprocessors and Microsystems, Vol. 24, No. 1, Mar. 2000, pp. 1-11. Click here for an electronic copy.
14. M. Burns, A. George, and B. Wallace, "Modeling and Simulative Performance Analysis of SMP and Clustered Computer Architectures," Simulation, Vol. 74, No. 2, Feb. 2000, pp. 84-96. Click here for an electronic copy.
15. M. Burns, A. George, and B. Wallace, "Simulative Performance Analysis of Gossip Failure Detection for Scalable Distributed Systems," Cluster Computing, Vol. 2, No. 3, Dec. 1999, pp. 207-217. Click here for an electronic copy.
16. A. George, J. Markwell, R. Fogarty, and M. Miars, "An Integrated Simulation Environment for Parallel and Distributed System Prototyping," Simulation, Vol. 72, No. 5, May 1999, pp. 283-294. Click here for an electronic copy.
17. A. George and S. Cook, Jr., "Distributed Simulation of Parallel DSP Architectures on Workstation Clusters," Simulation, Vol. 67, No. 2, Aug. 1996, pp. 94-105. Click here for an electronic copy.
18. A. George, "Simulating Microprocessor-based Parallel Computers using Processor Libraries," Simulation, Vol. 60, No. 1, Feb. 1993, pp. 37-42. Click here for an electronic copy.

Dissertations and theses:

1. Eric Grobelny, "FASE: the Fast and Accurate Simulation Environment for High-Performance Computing Systems and Applications," Ph.D. Dissertation, Major Professor: A. George, Spring 2008.
2. Jeremy D. Wills, "An Optical Component Library for Multi-Layer Network Simulations," BSEE Honors Thesis, Major Professor: A. George, Summer 2003.
3. Ian A. Troxel, "Design and Analysis of a Dynamically Reconfigurable Network Processor," MSECE Thesis, Major Professor: A. George, Fall 2002.
4. Matthew C. Chidester, "Parallel Simulation and Multiple-Path Execution Techniques for Chip-Multiprocessor Architectures," Ph.D. Dissertation, Major Professor: A. George, Summer 2001.
5. Mushtaq A. Sarwar, "On the Performance and Reliability of Fault-Tolerant Scalable Coherent Interface Networks," Ph.D. Dissertation, Major Professor: A. George, Fall 1999.
6. Sridharan Ranganathan, "Gossip-Style Failure Detection and Distributed Consensus for Scalable Heterogeneous Clusters," MSECE Thesis, Major Professor: A. George, Fall 1999.
7. Mark W. Burns, "Modeling and Simulative Analysis of Symmetric Multiprocessor and Clustered Computer Architectures," MSECE Thesis, Major Professor: A. George, Spring 1999.
8. Roger A. VanLoon, "High-Fidelity Modeling and Simulation of Myrinet System Area Networks," MSECE Thesis, Major Professor: A. George, Spring 1999.
9. Bradley A. Wallace, "Simulative Performance Analysis of Gossip Failure Detection for Scalable Distributed Systems," MSECE Thesis, Major Professor: A. George, Spring 1999.
10. Ryan B. Fogarty, "An Integrated Simulation Environment for Parallel and Distributed System Prototyping," MSECE Thesis, Major Professor: A. George, Fall 1998.
11. Matthew C. Chidester, "Specification and Simulation of a Directed Flow Control for Ring-Based, Real-Time Networking," MSECE Thesis, Major Professor: A. George, Summer 1998.
12. Michael D. Miars, "Simulation and Analysis of Vehicle Management Avionics System Architectures," MSEE Thesis, Major Professor: A. George, Fall 1996.
13. Robert W. Todd, "A Simulation Case Study of Proposed Real-Time Protocols based on the Scalable Coherent Interface," MSEE Thesis, Major Professor: A. George, Summer 1996.
14. Robert W. Todd, "Fundamental Coarse-Grain Modeling and Simulation of a Linear, Token-Passing Architecture for Smart Navy Aircraft Components/Systems (SNACS)," BSEE Honors Thesis, Major Professor: A. George, Spring 1995.
15. Steven W. Cook, Jr., "Distributed Simulation of DSP Multicomputers on Workstation Clusters," MSEE Thesis, Major Professor: A. George, Spring 1994.