What is SCI?
"SCI is the modern equivalent of a Processor-Memory-I/O bus and a Local
Area Network, combined and made parallel to support distributed multiprocessing
with very high bandwidth, very low latency, and a scalable architecture
that allows building large systems out of many inexpensive massproduced
building blocks. SCI originated as an offshoot from the IEEE Standard Futurebus+
project in 1988, when it became clear that coming microprocessors were
soon going to be too fast for any bus, even Futurebus+, to support cost-effectively
in multiprocessor configurations. The SCI group searched for some new approach
that would provide familiar bus-like services to the user but avoid the
bottlenecks inherent in physical buses; scale up to high-end supercomputer
performance; and support efficient software for parallel-processing systems
and applications."
-- Excerpt from http://www.SCIzzL.com/WhatIsSCI.html
- David B. Gustavson - Chair IEEE1596 Standards Committee.
The SCI standard is targeted towards increasing the bandwidth of backplane buses and became an IEEE standard in March of 1992. It improves on the bandwidth of buses by using high-speed, ring-connected, point-to-point links. With a link speed of 1 GB/s (i.e. a gigabyte per second), addressing for of up to 64K nodes, and a cache-coherence protocol for distributed shared-memory systems, the popularity of SCI for use in large multiprocessors has continued to increase.
SCI is used as a supplement to existing interconnects in multiprocessors. The reason for this conservative use of SCI is that the standard does not define a switch architecture, hence most SCI implementations remain proprietary. Sequent, Cray, and HP-Convex are among the parallel computer vendors that have developed proprietary implementations of SCI for their high-end systems. Sequent developed the IQ-link implemented in their Numa-Q 2000 system to connect Quads of four processors in a ring structure. Cray developed the SCX channel, also known as the GigaRing, capable of sustained bandwidths of 900MB/s half-duplex. The HP-Convex Exemplar Series uses the SCI-based Coherent Torroidal Interconnect (CTI) to interface hypernodes consisting of 8 processing units each.
SCI has also gained recognition in the workstation cluster market. To date, Dolphin Interconnect Solutions has emerged as the leading manufacturer of SCI adapter cards and switches for clusters. The Dolphin switch relies on an internal B-link bus as the switch fabric. The B-link is capable of a bandwidth ranging from 200MB/s to 400MB/s depending on the operating clock speed. Sun has adopted the Dolphin Interconnect implementation, dubbed CluStar, for their Enterprise Clusters. Recently, Dolphin introduced a dual-ported PCI/SCI adapter card to construct unidirectional torus topologies, the first of which is installed at the University of Paderborn in Germany. In other developments, Data General in collaboration with Dolphin Interconnect has developed a chipset for their AV20000 Enterprise server to interface SCI to Intel’s Standard High Volume (SHV) server nodes. In addition, Dolphin and Siemens jointly developed a PCI-SCI bridge to be used in the I/O subsystems of the Seimens RM600E Series Enterprise Servers.
The SCI Standard (IEEE1596) in PDF form (15MB)
Here is great set of slides used by Dr. Gustavson in his bi-annual SCI tutorial.
The SCI standard was developed to accommodate and use a common scalable-bus, technology-independent CSR architecture. The CSR standard defines a set of control and status registers for use in bus based systems. The word bus is used to define an interconnect and not the bus architecture. The purpose of the standard was to develop a flexible control and status register set that is scalable, independent of the bus system used, and which provides easy migration from one bus system to another. An added benefit is that software and firmware changes become minimal when changing or bridging bus systems. The CSR architecture was developed through the cooperative efforts of three IEEE working groups, P1394 Serial Bus, P896 Futurebus+, and P1596 Scalable Coherent Interface.
The CSR Architecture (IEEE 1212) in PDF form (7MB)
SCI at HCS
So what is HCS looking at SCI for?
How do I get started with SCI?
Go through the tutorial slides, and if they seem a little vague, start reading the SCI Standard. Chapters 1 and 3 describe the operation of SCI. Chapter 4 deals with the cache coherence protocols.
SCI Related Sites
SCIzzL - The Local Area Memory Port, Local Area MultiProcessor, Scalable Coherent Interface, and Serial Express Users, Developers, and Manufacturers Association. Contains the latest information on the world of SCI.
Dolphin Interconnect Solutions - Manufacturer of SCI node chips and switches primarity for clusters. Dolphin equipment has also been adapted for multiprocessor systems.
Interconnect Systems Solutions - First US-based SCI LincChip manufacturer.
University of Oslo - Most of the SCI research performed at the University of Oslo has dealt with SCI switches and bridges. A lot of this work has been incorporated into Dolphin's switches. The Physics department also produces several SCI-based prototype switches and bridges for data aqcuisition purposes.
European Laboratory for Particle Physics (CERN) - Working with the University of Oslo to create fast SCI-based data aqcusition systems.
University of Wisconsin - Madison - The SCI group was extremely active in the development of SCI. They are also responsible for the Kiloprocessor Extensions to SCI (IEEE 1596.2)
University of California - Santa Barbara - Currently doing research on SCI clusters and have implemented a version of active messages for SCI.
SCI Papers from Various Web Sources
High-performance Computing and Simulation Research Lab